1. Field of the Invention
The present invention relates to an apparatus and method for providing a bidirectional communications link between a master device and a slave device, and in particular to a mechanism for ensuring correct operation of the bidirectional communications link when subjected to a sequence of power down and power up operations.
2. Description of the Prior Art
It is known to design system-on-chip (SoC) integrated circuits by connecting together a plurality of functional circuit blocks using interconnect circuitry. As an example, the functional circuit blocks may include a processor core, a graphics processing unit, a memory controller, input/output interface circuitry etc. The interconnect circuitry may have the form of a wide parallel signal connection in which a plurality of multi-bit channels are provided passing in each direction. An example of such an interconnect architecture is the AXI interconnect architecture designed by ARM Limited of Cambridge, England. A problem with this approach as system-on-chip integrated circuits increase in complexity and size is that the parallel interconnect circuitry may include a disadvantageously large number of signal lines which can require routing over long distances within the system-on-chip integrated circuit thereby consuming a disadvantageous amount of circuit area and resource.
In order to address the above problem of routing wide parallel interconnect circuitry over relatively large distances within a SoC integrated circuit, it has been proposed to convert the parallel signals at the source into a plurality of data packets which can then be serially transmitted over a narrower interconnect. As an example, a full parallel interface of over 100 signal lines may be broken down into a plurality of narrower multi-bit data packets which are each transferred in turn in a time-division-multiplexed fashion over a narrower interconnect before being reassembled at the packet receiver into the full width parallel interface signals and applied to the destination circuitry. Such a form of narrower interconnect will also be referred to herein as a thin link interconnect.
It is known within some systems that the data source and the data destination may be operating in different clock domains. For example, a system-on-chip integrated circuit may include multiple clock domains using clocks of different frequencies. Some of the frequencies may vary depending upon the performance requirements of the circuitry within that domain at a particular point in time e.g. a processor core may have its clock frequency varied depending upon the processing workload it currently faces with a lower clock frequency being used when the workload is low in order to reduce power consumption. The clocks used to control the circuitry within different clock domains may be asynchronous from one another, and hence first-in-first-out buffers may be provided within the thin link interconnect when passing signals between asynchronous clock domains, the signals being captured into the buffers for resynchronising with the clock signal of the destination clock domain.
One way of managing transmission of signals which are received into buffers is to use a credit-based mechanism where the packet transmitter gates transmission of packets to the packet receiver based on credit information that it receives from the packet receiver indicative of available space within the buffers. For example a token signal may be used to indicate to the packet transmitter whether or not there is storage capacity within an associated first-in-first-out buffer. This token can be used as part of a flow control system that provides “back pressure” between the packet transmitter and the packet receiver so as to gate the packet transmitter from sending more data packets when there is insufficient storage capacity within a receiving first-in-first-out buffer to store those data packets for resynchronisation across the asynchronous clock boundary.
In some implementations, it will be necessary for the thin link interconnect to provide for bidirectional communication of data packets. Hence, when using the above-described credit-based mechanism, there will not only be data passing in both directions through the thin link interconnect, but there will also be credit signals passing in both directions.
Many modern SoC integrated circuits employ multiple power domains, allowing parts of the SoC to be powered down when not in use, in order to reduce power consumption. The presentation slides entitled “Network-on-Chip: the Future of SoC Power Management” produced by Arteris, and available on the Internet at the web address http://www.cdnusers.org/community/encounter/Resources/resources_design/overview/Dtp_cdnliveemea2006_arterisNOC.pdf, describes on slide 15 the possibility of powering down a power domain including a portion of an interconnect structure, indicating that the domain must be idle before power down is performed.
The paper “FlexiBuffer: Reducing Leakage Power in On-Chip Network Routers”, by G. Kim, J. Kim, and S. Yoo, DAC 2011, 5 to 10 Jun. 2011, San Diego, Calif., USA, explains how credit flow latency can affect system performance, and illustrates how power consumption can be reduced by sending an early credit. Further, the paper “Ultra Fine-Grained Run-Time Power Gating of On-Chip Routers for CMPs”, by F L Matsutani, et al., NOCS 2010, provides an overview on how power gating can be applied on a SOC, and also explains the importance of early wake up latency.
When the above described thin link interconnect structure is employed within a SoC employing multiple power domains, in addition to issues of wake up latency, a problem that arises is how to ensure correct operation of the thin link interconnect structure when either end of the thin link interconnect is subjected to power down and power up operations.